Instruction Set Principles - Computer Architecture: A Quantitative Approach - page 526

A few special registers can be transferred to and from the general-purpose registers. An
example is the floating-point status register, used to hold information about the results of
floating-point operations. There are also instructions for moving between an FPR and a GPR.
Data Types For MIPS
The data types are 8-bit bytes, 16-bit half words, 32-bit words, and 64-bit double words for in-
teger data and 32-bit single precision and 64-bit double precision for floating point. Half words
were added because they are found in languages like C and are popular in some programs,
such as the operating systems, concerned about size of data structures. They will also become
more popular if Unicode becomes widely used. Single-precision floating-point operands were
added for similar reasons. (Remember the early warning that you should measure many more
programs before designing an instruction set.)
The MIPS64 operations work on 64-bit integers and 32- or 64-bit floating point. Bytes, half
words, and words are loaded into the general-purpose registers with either zeros or the sign
bit replicated to fill the 64 bits of the GPRs. Once loaded, they are operated on with the 64-bit
integer operations.
Addressing Modes For MIPS Data Transfers
The only data addressing modes are immediate and displacement, both with 16-bit fields. Re-
gister indirect is accomplished simply by placing 0 in the 16-bit displacement field, and ab-
solute addressing with a 16-bit field is accomplished by using register 0 as the base register.
Embracing zero gives us four effective modes, although only two are supported in the archi-
tecture.
MIPS memory is byte addressable with a 64-bit address. It has a mode bit that allows soft-
ware to select either Big Endian or Litle Endian. As it is a load-store architecture, all references
between memory and either GPRs or FPRs are through loads or stores. Supporting the data
types mentioned above, memory accesses involving GPRs can be to a byte, half word, word,
or double word. The FPRs may be loaded and stored with single-precision or double-precision
numbers. All memory accesses must be aligned.
MIPS Instruction Format
Since MIPS has just two addressing modes, these can be encoded into the opcode. Following
the advice on making the processor easy to pipeline and decode, all instructions are 32 bits
with a 6-bit primary opcode. Figure A.22 shows the instruction layout. These formats are
simple while providing 16-bit fields for displacement addressing, immediate constants, or PC-
relative branch addresses.