Instruction Set Principles - Computer Architecture: A Quantitative Approach - page 525

A.9 Putting It All Together: The MIPS Architecture
In this section we describe a simple 64-bit load-store architecture called MIPS. The instruction
set architecture of MIPS and RISC relatives was based on observations similar to those covered
in the last sections. (In Section L.3 we discuss how and why these architectures became popu-
lar.) Reviewing our expectations from each section, for desktop applications:
■ Section A.2 —Use general-purpose registers with a load-store architecture.
■ Section A.3 —Support these addressing modes: displacement (with an address offset size of
12 to 16 bits), immediate (size 8 to 16 bits), and register indirect.
■ Section A.4 —Support these data sizes and types: 8-, 16-, 32-, and 64-bit integers and 64-bit
IEEE 754 floating-point numbers.
■ Section A.5 —Support these simple instructions, since they will dominate the number of in-
structions executed: load, store, add, subtract, move register-register, and shift.
■ Section A.6 —Compare equal, compare not equal, compare less, branch (with a PC-relative
address at least 8 bits long), jump, call, and return.
■ Section A.7 —Use fixed instruction encoding if interested in performance, and use variable
instruction encoding if interested in code size.
■ Section A.8 —Provide at least 16 general-purpose registers, be sure all addressing modes
apply to all data transfer instructions, and aim for a minimalist instruction set. This section
didn't cover floating-point programs, but they often use separate floating-point registers.
The justification is to increase the total number of registers without raising problems in the
instruction format or in the speed of the general-purpose register file. This compromise,
however, is not orthogonal.
We introduce MIPS by showing how it follows these recommendations. Like most recent
computers, MIPS emphasizes
■ A simple load-store instruction set
■ Design for pipelining efficiency (discussed in Appendix C ) , including a fixed instruction
set encoding
■ Efficiency as a compiler target
MIPS provides a good architectural model for study, not only because of the popularity of
this type of processor, but also because it is an easy architecture to understand. We will use
this architecture again in Appendix C and in Chapter 3 , and it forms the basis for a number of
exercises and programming projects.
In the years since the first MIPS processor in 1985, there have been many versions of MIPS
(see Appendix K). We will use a subset of what is now called MIPS64, which will often abbre-
viate to just MIPS, but the full instruction set is found in Appendix K.
Registers For MIPS
MIPS64 has 32 64-bit general-purpose registers (GPRs), named R0, R1,…, R31. GPRs are also
sometimes known as integer registers . Additionally, there is a set of 32 floating-point registers
FPRis named F0, F1,…, F31, which can hold 32 single-precision (32-bit) values or 32 double-
precision (64-bit) values. (When holding one single-precision number, the other half of the FPR
is unused.) Both single- and double-precision floating-point operations (32-bit and 64-bit) are
provided. MIPS also includes instructions that operate on two single-precision operands in a
single 64-bit floating-point register.
The value of R0 is always 0. We shall see later how we can use this register to synthesize a
variety of useful operations from a simple instruction set.