Thread-Level Parallelism - Computer Architecture: A Quantitative Approach - page 346

FIGURE 5.1 Basic structure of a centralized shared-memory multiprocessor based on
a multicore chip . Multiple processor-cache subsystems share the same physical memory,
typically with one level of shared cache, and one or more levels of private per-core cache. The
key architectural property is the uniform access time to all of the memory from all of the pro-
cessors. In a multichip version the shared cache would be omitted and the bus or interconnec-
tion network connecting the processors to memory would run between chips as opposed to
within a single chip
The alternative design approach consists of multiprocessors with physically distributed
memory, called distributed shared memory (DSM). Figure 5.2 shows what these multiprocessors
look like. To support larger processor counts, memory must be distributed among the pro-
cessors rather than centralized; otherwise, the memory system would not be able to support
the bandwidth demands of a larger number of processors without incurring excessively long
access latency. With the rapid increase in processor performance and the associated increase
in a processor's memory bandwidth requirements, the size of a multiprocessor for which dis-
tributed memory is preferred continues to shrink. The introduction of multicore processors
has meant that even two-chip multiprocessors use distributed memory. The larger number of
processors also raises the need for a high-bandwidth inter-connect, of which we will see ex-
amples in Appendix F. Both directed networks (i.e., switches) and indirect networks (typically
multidimensional meshes) are used.