Hardware Reference
In-Depth Information
For example, although a vector processor or GPU may be able to efficiently parallelize op-
erations on short vectors, the resulting grain size when the parallelism is split among many
threads may be so small that the overhead makes the exploitation of the parallelism prohibit-
ively expensive in an MIMD.
Existing shared-memory multiprocessors fall into two classes, depending on the number of
processors involved, which in turn dictates a memory organization and interconnect strategy.
We refer to the multiprocessors by their memory organization because what constitutes a
small or large number of processors is likely to change over time.
The first group, which we call symmetric (shared-memory) multiprocessors (SMPs), or central-
ized shared-memory multiprocessors , features small numbers of cores, typically eight or fewer.
For multiprocessors with such small processor counts, it is possible for the processors to share
a single centralized memory that all processors have equal access to, hence the term symmet-
ric. In multicore chips, the memory is effectively shared in a centralized fashion among the
cores, and all existing multicores are SMPs. When more than one multicore is connected, there
are separate memories for each multicore, so the memory is distributed rather than central-
ized.
SMP architectures are also sometimes called uniform memory access (UMA) multiprocessors,
arising from the fact that all processors have a uniform latency from memory, even if the
memory is organized into multiple banks. Figure 5.1 shows what these multiprocessors look
like. The architecture of SMPs is the topic of Section 5.2 , and we explain the approach in the
context of a multicore.
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