Data-Level Parallelism in Vector, SIMD, and GPU Architectures - Computer Architecture: A Quantitative Approach - page 264

■ Vector load/store unit —The vector memory unit loads or stores a vector to or from memory.
The VMIPS vector loads and stores are fully pipelined, so that words can be moved
between the vector registers and memory with a bandwidth of one word per clock cycle,
after an initial latency. This unit would also normally handle scalar loads and stores.
■ A set of scalar registers —Scalar registers can also provide data as input to the vector func-
tional units, as well as compute addresses to pass to the vector load/store unit. These are
the normal 32 general-purpose registers and 32 floating-point registers of MIPS. One input
of the vector functional units latches scalar values as they are read out of the scalar register
ile.
Figure 4.3 lists the VMIPS vector instructions. In VMIPS, vector operations use the same
names as scalar MIPS instructions, but with the leters “VV” appended. Thus, ADDVV.D is an ad-
dition of two double-precision vectors. The vector instructions take as their input either a pair
of vector registers ( ADDVV.D ) or a vector register and a scalar register, designated by appending
“VS” ( ADDVS.D ). In the later case, all operations use the same value in the scalar register as one
input: The operation ADDVS.D will add the contents of a scalar register to each element in a vec-
tor register. The vector functional unit gets a copy of the scalar value at issue time. Most vector
operations have a vector destination register, although a few (such as population count) pro-
duce a scalar value, which is stored to a scalar register.