Data-Level Parallelism in Vector, SIMD, and GPU Architectures - Computer Architecture: A Quantitative Approach - page 265

FIGURE 4.3 The VMIPS vector instructions, showing only the double-precision
floating-point operations . In addition to the vector registers, there are two special registers,
VLR and VM , discussed below. These special registers are assumed to live in the MIPS copro-
cessor 1 space along with the FPU registers. The operations with stride and uses of the index
creation and indexed load/store operations are explained later.
The names LV and SV denote vector load and vector store, and they load or store an entire
vector of double-precision data. One operand is the vector register to be loaded or stored; the
other operand, which is a MIPS general-purpose register, is the starting address of the vector
in memory. As we shall see, in addition to the vector registers, we need two additional special-
purpose registers: the vector-length and vector-mask registers. The former is used when the
natural vector length is not 64 and the later is used when loops involve IF statements.
The power wall leads architects to value architectures that can deliver high performance
without the energy and design complexity costs of highly out-of-order superscalar processors.
Vector instructions are a natural match to this trend, since architects can use them to increase
performance of simple in-order scalar processors without greatly increasing energy demands
and design complexity. In practice, developers can express many of the programs that ran well
on complex out-of-order designs more efficiently as data-level parallelism in the form of vec-
tor instructions, as Kozyrakis and Paterson [2002] showed.