Instruction-Level Parallelism and Its Exploitation - Computer Architecture: A Quantitative Approach - page 194

in half a clock cycle, so that two instructions can be processed in one clock cycle; this approach
cannot be easily extended to handle four instructions per clock, unfortunately.
A second alternative is to build the logic necessary to handle two or more instructions at
once, including any possible dependences between the instructions. Modern superscalar pro-
cessors that issue four or more instructions per clock may include both approaches: They both
pipeline and widen the issue logic. A key observation is that we cannot simply pipeline away
the problem. By making instruction issues take multiple clocks because new instructions are
issuing every clock cycle, we must be able to assign the reservation station and to update the
pipeline tables, so that a dependent instruction issuing on the next clock can use the updated
information.
This issue step is one of the most fundamental botlenecks in dynamically scheduled super-
scalars. To illustrate the complexity of this process, Figure 3.18 shows the issue logic for one
case: issuing a load followed by a dependent FP operation. The logic is based on that in Figure
3.14 on page 191, but represents only one case. In a modern superscalar, every possible com-
bination of dependent instructions that is allowed to issue in the same clock cycle must be con-
sidered. Since the number of possibilities climbs as the square of the number of instructions
that can be issued in a clock, the issue step is a likely botleneck for attempts to go beyond four
instructions per clock.