Instruction-Level Parallelism and Its Exploitation - Computer Architecture: A Quantitative Approach - page 193

with speculation with one issue per clock, except that the issue and completion logic must be
enhanced to allow multiple instructions to be processed per clock.
FIGURE 3.17 The basic organization of a multiple issue processor with speculation . In
this case, the organization could allow a FP multiply, FP add, integer, and load/store to all is-
sues simultaneously (assuming one issue per clock per functional unit). Note that several
datapaths must be widened to support multiple issues: the CDB, the operand buses, and, crit-
ically, the instruction issue logic, which is not shown in this figure. The last is a difficult prob-
lem, as we discuss in the text.
Issuing multiple instructions per clock in a dynamically scheduled processor (with or
without speculation) is very complex for the simple reason that the multiple instructions may
depend on one another. Because of this the tables must be updated for the instructions in par-
allel; otherwise, the tables will be incorrect or the dependence may be lost.
Two different approaches have been used to issue multiple instructions per clock in a dy-
namically scheduled processor, and both rely on the observation that the key is assigning a
reservation station and updating the pipeline control tables. One approach is to run this step