Instruction-Level Parallelism and Its Exploitation - Computer Architecture: A Quantitative Approach - page 195

FIGURE 3.18 The issue steps for a pair of dependent instructions (called 1 and 2)
where instruction 1 is FP load and instruction 2 is an FP operation whose first operand
is the result of the load instruction; r1 and r2 are the assigned reservation stations for
the instructions; and b1 and b2 are the assigned reorder buffer entries . For the issuing in-
structions, rd1 and rd2 are the destinations; rs1 , rs2 , and rt2 are the sources (the load only has
one source); r1 and r2 are the reservation stations allocated; and b1 and b2 are the assigned
ROB entries. RS is the reservation station data structure. RegisterStat is the register data struc-
ture, Regs represents the actual registers, and ROB is the reorder buffer data structure. Notice
that we need to have assigned reorder buffer entries for this logic to operate properly and re-
call that all these updates happen in a single clock cycle in parallel, not sequentially!
We can generalize the detail of Figure 3.18 to describe the basic strategy for updating the is-
sue logic and the reservation tables in a dynamically scheduled superscalar with up to n issues
per clock as follows:
1. Assign a reservation station and a reorder buffer for every instruction that might be issued
in the next issue bundle. This assignment can be done before the instruction types are
known, by simply preallocating the reorder buffer entries sequentially to the instructions
in the packet using n available reorder buffer entries and by ensuring that enough reserva-
tion stations are available to issue the whole bundle, independent of what it contains. By