Memory Hierarchy Design - Computer Architecture: A Quantitative Approach - page 124

even predictions about the relative miss rates of integer and floating-point-intensive programs
can be wrong as mcf and sphnix3 remind us!
FIGURE 2.26 Instruction and data misses per 1000 instructions as cache size varies
from 4 KB to 4096 KB . Instruction misses for gcc are 30,000 to 40,000 times larger than lu-
cas, and, conversely, data misses for lucas are 2 to 60 times larger than gcc. The programs
gap, gcc, and lucas are from the SPEC2000 benchmark suite.
Pitfall Simulating Enough Instructions To Get Accurate Performance Measures Of
The Memory Hierarchy
There are really three pitfalls here. One is trying to predict performance of a large cache using
a small trace. Another is that a program's locality behavior is not constant over the run of the
entire program. The third is that a program's locality behavior may vary depending on the in-
put.
Figure 2.27 shows the cumulative average instruction misses per thousand instructions for
ive inputs to a single SPEC2000 program. For these inputs, the average memory rate for the
irst 1.9 billion instructions is very different from the average miss rate for the rest of the exe-
cution.