MODELING AND BUDGETING OF TIMING JITTER AND NOISE - Advanced Signal Integrity for High-Speed Digital Design - page 548

<10 − 14

BER:

10 − 14 -10 − 12

10 − 12 -10 − 10

10 − 10 -10 − 8
10 − 8 -10 − 6
>10 − 6

0 10 20 30 40 50 60 70 80 90 100

Sampling time (ps)

Figure 13-4 Example BER contours.

would degrade the eye opening are treated as bounded sources that do not exceed
a specified amount. An example of an interface design based on the worst-case
approach is the AGP 8X mode interface, which we describe here [Intel, 2002].
The AGP 8X mode is a 533-Mb/s source synchronous interface, which is
shown in Figure 13-5a. The AGP source synchronous transmitter sends a clock
signal along with a group of 16 data signals. The delay line in the transmitting
chip offsets the clock signal by 90 ◦ from the data signal in order to center it
in the data eye. Source synchronous designs achieve high performance by pre-
serving the clock-to-data phase relationship. Doing so requires that the delays of
the data signals be matched to those of the clock signal, which is accomplished
by using identical transmitters and by matching the interconnect lengths. In the-
ory, the maximum transmission rate of a source synchronous system is limited
only by the setup-and-hold window of the receiver, which is described by Dally
and Poulton [1998]. In practice, however, variation in the delay of the trans-
mitters, interconnects, and receivers will reduce maximum achievable rate to a
substantially lower value. For example, sources of variation in the transmitter
delay include differences in the clock distribution path to the various circuits,
process variation within the chip, and noise. Timing variation terms for source
synchronous interfaces are typically specified as relative delays between the data
and clock signals, so they include variations of each.