MODELING AND BUDGETING OF TIMING JITTER AND NOISE - Advanced Signal Integrity for High-Speed Digital Design - page 547

50 ps

250

200

150

100

50

0 2.5 V/ns Eye Mask

− 50

− 100

− 150

− 200

− 250

70 80 90 100 110 120 130 140 150 160 170 180 190 200 210 220 230

Time (ps)

Figure 13-3 Example eye diagram and spec eye mask.

where ( t s , v s ) represents the relative voltages and times at which the signal is
sampled, N err is the number of erroneous bits received, and N is the number of
bits transmitted over the same time interval.
Equation (13-1) suggests that the BER depends on when we sample the data
and at what voltage level (i.e., the sampling point position). By varying the sample
point, we can generate a diagram that consists of a set of contours at a set of
BER values, as shown in Figure 13-4. Ideally, the receiver will sample the data
signal in the center of the eye. However, jitter and noise can cause nonideal data
sampling, which can result in transmission errors. For example, if the receiver
samples in the middle of the data eye, at the point corresponding to 50 mV and
50 ps in the figure, the error rate is less than 1 bit in 100 trillion (10 − 14 ). On the
other hand, sampling at the edge of the eye, such as 10 mV and 10 ps, gives a
BER in excess of 1 bit per million (10 − 6 ). At a transmission rate of 10 Gb/s, a
BER of 10 − 14 will produce one error in approximately 2 hours and 45 minutes,
while the 10 − 6 BER results in 10,000 errors per second! Communicating at high
bit error ratios requires that error detection and correction capabilities be designed
into the I/O circuits, which adds complexity and consumes power. Errors also
degrade performance, as they must be detected and then the data re-transmitted.
We discuss BER estimation in Section 13.2.
As a final thought, we note that the eye diagram applies to both single-ended
and differential interfaces. In the case of a differential interface, the eye diagram
should plot the differential voltage ( v diff = v − v ) at the receiver.

13.2 BIT ERROR RATE

13.2.1 Worst-Case Analysis

Historically, timing analysis for signaling interfaces in PC systems has employed
a worst-case methodology. In this approach, all sources of timing uncertainty that