MODELING AND BUDGETING OF TIMING JITTER AND NOISE - Advanced Signal Integrity for High-Speed Digital Design - page 549

Tx Chip

x16

D Q D Q

Data

Delay
Line

I/O
Clock

Rx Chip

(a)

UI
1875 ps

D t TxSu
410 ps

D t chanSu
442.5 ps

D t chanH
267.5 ps

D t TxH
460 ps

D t RxSu
85 ps

D t RxH
210 ps

ideal clock position

(b)

Figure 13-5 AGP 2.0 8X mode source synchronous system timings: (a) system config-
uration; (b) worst-case timing budget.

The worst-case timing equations for the AGP source synchronous link are

UI
2

t marSu = − t TxSu − t chanSu − t RxSu (13-2)

UI
2

t marH = − t TxH − t chanH − t RxH (13-3)

where t marSu and t marH = timing margins for the setup and hold

conditions (ps)

UI = unit interval, which is the width of a single bit

(ps)

t TxSu and t TxH = variation in transmitter delay relative to the

clock path for the setup and hold cases (ps)

t IntSu and t IntH = variation in interconnect delay relative to the

clock path for the setup and hold cases (ps)

t RxSu and t RxH = variation in receiver delay relative to the clock

path for the setup and cases (ps)

At 533 Mb/s, the length of a single bit, known as the unit interval (UI),
is 1875 ps. The AGP 8X specification at the receiver is 85 ps for the setup
case and 210 ps for the hold case. The spec budgets 410 ps for the worst-case
variation of the transmitter delay for the data edge that precedes the clock (the