Hardware Reference
In-Depth Information
The original 3GIO code name was derived from the fact that this new bus specification
was designed to initially augment and eventually replace the previously existing ISA/
AT-Bus (first-generation) and PCI (second-generation) bus architectures in PCs. Each of
the first two generations of PC bus architectures was designed to have a 10-to-15-year
useful life in PCs. In being adopted and approved by the PCI-SIG, PCI Express is now
destined to be the dominant PC bus architecture designed to support the increasing band-
width needs in PCs over the next 10-15 years.
The key features of PCI Express are as follows:
• Compatibility with existing PCI enumeration and software device drivers.
• Physical connection over copper, optical, or other physical media to allow for future
encoding schemes.
• Maximum bandwidth per pin allows for small form factors, reduced cost, simpler
board designs and routing, and reduced signal integrity issues.
• Embedded clocking scheme that enables easy frequency (speed) changes compared to
synchronous clocking.
• Bandwidth (throughput) that increases easily with frequency and width (lane) in-
creases.
• Low latency suitable for applications requiring isochronous (time-sensitive) data de-
livery, such as streaming video.
• Hot-plugging and hot-swapping capabilities.
• Power management capabilities.
PCI Express is another example of how the PC has moved from parallel to serial inter-
faces. Earlier generation bus architectures in the PC have been of a parallel design, in
which multiple bits are sent simultaneously over several pins in parallel. The more bits
sent at a time, the faster the bus throughput is. The timing of all the parallel signals must
be the same, which becomes more and more difficult to do over faster and longer connec-
tions. Even though 32 bits can be transmitted simultaneously over a bus such as PCI or
AGP, propagation delays and other problems cause them to arrive slightly skewed at the
other end, resulting in a time difference between when the first and last of all the bits ar-
rive.
A serial bus design is much simpler, sending 1 bit at a time over a single wire, at much
higher rates of speed than a parallel bus would allow. By sending the bits serially, the tim-
ingofindividualbitsorthelengthofthebusbecomesmuchlessofafactor.Bycombining
multipleserialdatapaths,evenfasterthroughputscanberealizedthatdramaticallyexceed
the capabilities of traditional parallel buses.
