Hardware Reference
In-Depth Information
PCI Express is a fast serial bus design that is backward compatible with current PCI par-
allel bus software drivers and controls. In PCI Express, data is sent full duplex (simultan-
eously operating one-way paths) over two pairs of differentially signaled wires called a
lane
. Each lane allows for about 250MBps throughput in each direction initially, and the
designallowsforscalingfrom1to2,4,8,16,or32lanes.Forexample,ahigh-bandwidth
configuration with 16 lanes allowing 16 bits to be sent in each direction simultaneously
would allow up to 4,000MBps bandwidth each way. PCIe 2.0 increases the transfer rate
to 500MBps per lane, or 8,000MBps for an x16 connector. This compares to PCI, which
has only 133MBps bandwidth (one way at a time).
Figure 4.43
compares the PCI Express
x1-x16 connectors. Note that the PCI Express x4 and x8 connectors shown in this figure
are intended primarily for use in servers.
Figure 4.43
PCI Express x1, x4, x8, and x16 slots.
PCI Express uses an IBM-designed 8-bit-to-10-bit encoding scheme, which allows for
self-clocked signals that will easily allow future increases in frequency. The starting fre-
quency is 2.5GHz, and the specification allows increasing up to 10GHz in the future,
which is about the limit of copper connections. By combining frequency increases with
the capability to use up to 32 lanes, PCI Express is capable of supporting future band-
widths up to 32GBps.
PCI Express is designed to augment and replace many of the buses currently used in PCs.
It is not only be a supplement to (and the replacement for) PCI slots, but can also be used
to replace the existing Intel hub architecture, HyperTransport, and similar high-speed in-
terfaces between motherboard chipset components. Additionally, it replaces video inter-
