Hardware Reference
In-Depth Information
when searching for a specific location in the cache. In essence, each set in an
n
-way set
associative cache is a subcache that has associations with each main memory address. As
the number of subcaches or sets increases, eventually the cache becomes fully associat-
ive—a situation in which any memory address can be stored in any cache line location.
In that case, an
n
-way set associative cache is a compromise between a fully associative
cache and a direct-mapped cache.
In general, a direct-mapped cache is the fastest at locating and retrieving data from the
cache because it has to look at only one specific tag address for a given memory address.
However, it also results in more misses overall than the other designs. A fully associative
cache offers the highest hit ratio but is the slowest at locating and retrieving the data be-
causeithasmanymoreaddresstagstocheckthrough.An
n
-waysetassociative cacheisa
compromisebetweenoptimizingcachespeedandhitratio,butthemoreassociativitythere
is, the more hardware (tag bits, comparator circuits, and so on) is required, making the
cache more expensive. Obviously, cache design is a series of trade-offs, and what works
best in one instance might not work best in another. Multitasking environments such as
Windows are good examples of environments in which the processor needs to operate on
different areas of memory simultaneously and in which an
n
-way cache can improve per-
formance.
Thecontentsofthecachemustalwaysbeinsyncwiththecontentsofmainmemorytoen-
sure that the processor is working with current data. For this reason, the internal cache in
the 486 family was a
write-through
cache. Write-through means that when the processor
writes information to the cache, that information is automatically written through to main
memory as well.
By comparison, Pentium and later chips have an internal write-back cache, which means
that both reads and writes are cached, further improving performance.
Another feature of improved cache designs is that they are
nonblocking
. This is a tech-
nique for reducing or hiding memory delays by exploiting the overlap of processor op-
erations with data accesses. A nonblocking cache enables program execution to proceed
concurrently with cache misses as longas certain dependency constraints are observed. In
other words, the cache can handle a cache miss much better and enable the processor to
continue doing something nondependent on the missing data.
The cache controller built into the processor also is responsible for watching the memory
bus when alternative processors, known as
bus masters
, control the system. This process
of watching the bus is referred to as
bus snooping
. If a bus master device writes to an
area of memory that also is stored in the processor cache currently, the cache contents and
memory no longer agree. The cache controller then marks this data as invalid and reloads
the cache during the next memory access, preserving the integrity of the system.
