Hardware Reference
In-Depth Information
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Cache Organization
You know that cache stores copies of data from various main memory addresses. Because
the cache cannot hold copies of the data from all the addresses in main memory simul-
taneously, there has to be a way to know which addresses are currently copied into the
cache so that, if we need data from those addresses, it can be read from the cache rather
than from the main memory.This function is performed byTag RAM, which is additional
memory in the cache that holds an index of the addresses that are copied into the cache.
Each line of cache memory has a corresponding address tag that stores the main memory
addressofthedatacurrentlycopiedintothatparticularcacheline.Ifdatafromaparticular
main memory address is needed, the cache controller can quickly search the address tags
to see whether the requested address is currently being stored in the cache (a hit) or not (a
miss). If the data is there, it can be read from the faster cache; if it isn't, it has to be read
from the much slower main memory.
Various ways of organizing or mapping the tags affect how cache works. A cache can be
mapped as fully associative, direct-mapped, or set associative.
In a
fully associative mapped cache
, when a request is made for data from a specific main
memory address, the address is compared against all the address tag entries in the cache
tagRAM.Iftherequestedmainmemoryaddressisfoundinthetag(a
hit
),thecorrespond-
ing location in the cache is returned. If the requested address is not found in the address
tag entries, a
miss
occurs, and the data must be retrieved from the main memory address
instead of the cache.
Ina
direct-mapped cache
,specificmainmemoryaddressesarepreassignedtospecificline
locations in the cache where they will be stored. Therefore, the tag RAM can use fewer
bits because when you know which main memory address you want, only one address tag
needs to be checked, and each tag needs to store only the possible addresses a given line
can contain. This also results in faster operation because only one tag address needs to be
checked for a given memory address.
A
set associative cache
is a modified direct-mapped cache. A direct-mapped cache has
only one set of memory associations, meaning a given memory address can be mapped
into(orassociatedwith)onlyaspecificgivencachelinelocation.Atwo-waysetassociat-
ive cache has two sets, so that a given memory location can be in one of two locations. A
four-way set associative cache can store a given memory address into four different cache
line locations (or sets). By increasing the set associativity, the chance of finding a value
increases; however, it takes a little longer because more tag addresses must be checked
