Hardware Reference
In-Depth Information
AllPCprocessordesignsthatsupportcachememoryincludeafeatureknownasa
transla-
tion lookaside buffer
(TLB)toimproverecoveryfromcachemisses.TheTLBisatablein-
side the processor that stores information about the location of recently accessed memory
addresses. The TLB speeds up the translation of virtual addresses to physical memory ad-
dresses.
Asclockspeedsincrease,cycletimedecreases.Newersystemsnolongerusecacheonthe
motherboard because the faster system memory used in modern systems can keep upwith
the motherboard speed. Modern processors integrate the L2 cache into the processor die
just like the L1 cache, and most recent models include on-die L3 as well. This enables the
L2/L3 to run at full-core speed because it is now part of the core.
Processor Features
As new processors are introduced, new features are continually added to their architec-
tures to improve everything from performance in specific types of applications to the reli-
ability of the CPU as a whole. The next few sections look at some of these technologies.
System Management Mode (SMM)
Spurredoninitiallybytheneedformorerobustpowermanagementcapabilitiesinmobile
computers, Intel and AMD began adding
System Management Mode
(SMM) to its pro-
cessors during the early 1990s. SMM is a special-purpose operating mode provided for
handling low-level system power management and hardware control functions. SMM of-
fersanisolatedsoftwareenvironmentthatistransparenttotheOSorapplicationssoftware
and is intended for use by system BIOS or low-level driver code.
SMM was introduced as part of the Intel 386SL mobile processor in October 1990. SMM
laterappearedaspartofthe486SLprocessorinNovember1992,andintheentire486line
starting in June 1993. SMM was notably absent from the first Pentium processors when
they were released in March 1993; however, SMM was included in all 75MHz and faster
Pentium processors released on or after October 1994. AMD added SMM to its enhanced
Am486 and K5 processors around that time as well. All other Intel and AMD x86-based
processors introduced since that time also have incorporated SMM.
SMM is invoked by signaling a special interrupt pin on the processor, which generates
a System Management Interrupt (SMI), the highest priority nonmaskable interrupt avail-
able. When SMM starts, the context or state of the processor and currently running pro-
grams are saved. Then the processor switches to a separate dedicated address space and
executes the SMM code, which runs transparently to the interrupted program as well as
any other software on the system. Once the SMM task is complete, a resume instruction
