Image Processing Reference
In-Depth Information
(a)
φV1
φV2
φV3
φV4
φ1
φ2
φ3
φ4
Transfer electrode
(polysilicon, etc.)
n
-
Gate-insulating film
(SiO
2
, Si
3
N
4
,
etc.)
(buried channel)
Silicon substrate
p
Charge
packet
(b)
t
1-1
t
1-2
t
1-3
t
1-4
t
1-5
t
1-6
t
1-7
t
1-8
t
2-1
FIGURE 5.2
Four-phase CCD: (a) cross-sectional view; (b) schematic diagram of charge transfer.
H
φ1
L
H
φ2
L
H
φ3
L
H
φ4
L
t
1-1
t
1-2
t
1-3
t
1-4
t
1-5
t
1-6
t
1-7
t
1-8
t
2-1
FIGURE 5.3
Driving clock pulse of overlapping four-phase CCD.
