Image Processing Reference
In-Depth Information
TABLE 5.1
Devices for Each Functional Element in Each Sensor Type
(3) Charge Quantity
Measuring Part
Type
(1) Sensor Part
(2) Scanning Part
CCD sensor
pn -junction PD, photogate
CCD
FDA /sensor chip (common)
MOS sensor
pn -junction PD, photogate
Shift register/decoder
and MOSFET switch
JFET amplifier (off-chip
amplifier)
CMOS sensor
pn -junction PD, photogate
Shift register/decoder
and MOSFET switch
FDA/pixel (individual)
electrodes are replaced with one electrode, as in Figure 5.1b. By applying positive voltage
to another independent electrode, positive and negative charges are stored in another and
one electrode of the capacitor. By shifting one of the independent electrodes to which posi-
tive voltage is applied to the next electrode, negaitive charges stored at the opposite posi-
tion in the common electrode also shift to the position corresponding to the next electrode,
as shown in Figure 5.1b. That is, charges are transferred.
In real devices, the silicon substrate plays the role of the commonly connected elec-
trodes, on which a polycrystalline silicon (polysilicon) layer is formed. This creates further
electrodes by sandwiching a gate-insulating film such as silicon dioxide (SiO 2 ) or silicon
nitride (Si 3 N 4 ) between them, as shown in Figure 5.2a.
The electrodes are separated into four groups, in each of which electrodes are connected
periodically to all four electrodes, as shown in Figure 5.2a, and to which one of the clock
pulses of ϕ1, ϕ2, ϕ3, and ϕ4 in Figure 5.3 is applied. The operation proceeds as shown in
Figure 5.2b. At time t 1−1 , positive voltage is applied to electrodes ϕV1 and ϕV2 to store
charge packet in the channel potential well of the electrodes, and voltage is also applied
to the next electrode, ϕV3, to distribute charges to the channel at t 1−2 . By decreasing the
voltage applied to electrode ϕV1, the charge packet ranges under ϕV2 and ϕV3 at time
t 1−3 , that is, charge packet has been transferred by one electrode. Then, the same process
is repeated till the charge packet is transferred to a specific position. The mode shown in
Figure 5.2 is named four-phase CCD because of the four transfer clock pulses. Since CCD
is the capacitor, the maximum charge quantity that can be stored is in proportion to the
gate electrode area. In the mode shown in Figure 5.2, the charge packet is stored in at least
two electrode channels. This is desirable to increase the maximum charge quantity, which
is directly related to dynamic range performance of the sensor. On the other hand, a time
length of four clocks from t 1−1 to t 1−5 is necessary to transfer charges to the next stage. The
time length of eight clocks from t 1−1 to t 2−1 is needed to complete the charge transfer of one
cycle; therefore this mode is not suitable for high-speed transfer application.
(a)
(b)
FIGURE 5.1
(a,b) Schematic diagram of operational principle of CCD.
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