Image Processing Reference
In-Depth Information
φ
sd
φ
1d
V
in
φ
INI
C
2
(=
C
)
Sub-ADC
DAC
C
1a
(=
C
/2)
φ
0
V
RCH
φ
N
φ
S
V
RH
-
D
1
φ
2
+
φ
MS
-
-
V
RCL
D
0
+
φ
P
V
RL
φ
1
C
1b
(=C/2)
+
φ
N
Control
OTA
φ
P
V
COM
logic
φ
MS
FIGURE 5.61
Circuit configuration of a 13-bit cyclic column-parallel ADC. (Reprinted with permission from Park, J.,
Aoyama, S., Watanabe, T., Isobe, K., and Kawahito, S.,
Transactions on Electron Devices
, 56, 2414-2422, 2009.)
D
D
2
Readout circuits [top]
2.25 µm 2-shared
Pixel array
1696(V) × 1212(H)
∆Σ Modulator
Decimation filter with CDS
D
3
SRAM buffer memory
D
4
Column decoder
Readout circuits [bottom]
FIGURE 5.62
Block diagram of a 12-bit ΔΣ ADC sensor. (Reprinted with permission from Chae, Y., Cheon, J., Lim, S., Lee, D.,
Kwon, M., Yoo, K., Jung, W., Lee, D., Ham, S., and Han, G.,
Proceedings of the IEEE International Solid-State Circuits
Conference, Digest of Technical Papers
, 22.1, pp. 394-395, San Francisco, CA, 2010.)
