Image Processing Reference
In-Depth Information
Since it has reflection symmetry in the horizontal direction, horizontal misalignments are
apt to give opposite effects to left-side and right-side pixels, that is, performances differ
between even and odd columns. There is an example of an eight-shared pixel sensor
37
by
sharing two pixels horizontally and four pixels vertically.
Movements of charges in shared pixel architecture are realized by connecting individ-
ual parts by metal wiring. This is an effectual measure for pixel shrinkage for CMOS sen-
sors that CCDs cannot use. On the other hand, it might be possible to recognize the CCD
as the ultimate shared pixel sensor, because only one FDA is shared by all pixels through
noiseless connections.
5.3.3 Progress in CMOS Sensors
As just described, pixel configuration and device constitution of CMOS sensors have
converged, pursuing an improvement in performance level to compete against CCDs.
More specifically, a 4-Tr pixel configuration with a buried/pinned PD and column CDS
circuit has been adopted. By reducing pixel noise in this manner, it becomes more impor-
tant to suppress noise of the following read circuits. An inevitable approach for image
sensors was to improve SNR by noise reduction in the analog domain circuit as the first
step. Subsequently, along with noise reduction and speeding up through digitization of
light intensity signal, sensitivity improvements by making effective use of incident light
are being approached.
5.3.3.1 Noise Reduction Circuits in Analog Output Sensor
Signal amplification forms the basis of reduction of impact of noise of the following cir-
cuits. Therefore, newly added FPN caused by new amplification is removed by additional
FPN cancelation circuits.
5.3.3.1.1 Amplifying Noise Canceller
Since the configuration is an analog circuit, charge quantity multiplied by pixel amplifier
drives the following circuit as the input charge quantity at the input part. Although it is
desirable to amplify as much as possible in the earlier stage before new noises are added,
this often fails because of the limitations of the available voltage range and capacitance
volume. A proposed method to reduce the impact of noise after a CDS circuit is column
amplifier configuration. While it is possible to arrange an amplifier before or after the
CDS circuit in Figure 5.46, the proposal is a circuit in which the vertical signal line is fol-
lowed by a column amplifier and there is an offset variation canceling function,
38
shown
in Figure 5.50.
When FD is reset, switches ϕ
1
and ϕ
2
in the column amplifying noise canceller are made
on-state to set the input part of the column amplifier as clamped. After ϕ
2
is changed to
off-situation, the readout pulse is applied to TX to transfer signal charges in PD to FD, and
amplified difference signal is output by the column amplifier. The voltage gain
G
of the
column amplifier is given by
G
=
C
1
/
C
2
. The higher the gain is, the higher the noise sup-
pression effect is. But this is meaningless if the amplified signal saturates the voltage range
of the circuit. Moreover, higher gain is necessary for a low-level signal itself to obtain a
higher SNR. Therefore, the column amplifier selects gain adaptively by choosing the best
capacitance as
C
2
.
In this configuration, noise of the column amplifier itself, pixel amplifier, and noise
canceller are suppressed as well as reduction effects of noise impact of substantial-stage
