Environmental Engineering Reference
In-Depth Information
FPGA Technology:
Development Tools
phase. Software code verification is performed
according to verification plan and testing plans
which should be developed and approved before
actions on software code verification.
Aldec Advanced Lint (ALINT™) tool can help
to detect the design problems early in life cycle,
including poor coding styles, improper clock and
reset management, simulation, synthesis problems,
poor testability and source code issues throughout
the design flow. ALINT™ is a programmable de-
sign and coding guideline checker that speeds up
development of complex system-on-chip designs.
Certain rules may be parameterized to fine-tune
custom checking policy. Policies combined with
various ALINT settings allow development of
unique rules checking framework for each design.
VHDL functional testing can be performed
with ModelSim Altera tool, which uses either
Verilog HDL or VHDL design files, including
models for the library of parameterized modules
and Altera megafunctions, to generate a functional
simulation output of the design based on the set
of stimulus applied by the user. Once the design
is verified to be functionally correct, the next step
is to perform implementation stage (synthesize
the design and use the Quartus II software for
place-and-route).
ModelSim-Altera software version is com-
patible with the specific Quartus II tool version.
Proper verification of designs at the functional and
post place-and-route stages using the ModelSim-
Altera software helps ensure design functionality
and, ultimately, a quick time-to-market.
Typically, implementation includes the fol-
lowing stages
During development activities, the use of proven
tools is preferred over manual methods. Moreover,
for development of safety critical I&C systems,
software-based tools shall be purchased only
from long-established vendors with a good track
record of CM, V&V, problem notification and
resolution, including help & training materials.
Software tools should be selected and evaluated
before their using in lifecycle processes.
One of the tools that can be used in develop-
ment activities for FPGA-based NPP I&C systems
is IDE Quartus II. It supports design and imple-
mentation stages, including VHDL coding, RTL
synthesis, Netlist synthesis, Placement&Routing,
Static timing analysis, and Bitstream generation.
It also supports hardware and functional block
libraries VHDL design entry, graphical-based
design entry methods, and integrated system-level
design tools. It integrates design, synthesis, place-
and-route, and verification into a development
environment.
IDE Quartus II from Altera has a wide range
of capabilities such as design entry, simulation,
synthesis, verification, and device programming.
Generally IDE Quartus II as FPGA design software
is widely used in different industries: military,
medical equipment manufacturing, automotive
electronic manufacturing, financial, bioscience,
etc.
I&C system Design Entry is performed accord-
ing to I&C system Requirements Specifications.
The desired circuit is specified either by means
of a schematic diagram, or by using a Hardware
description language, such as VHDL or Verilog.
Inputs documents for design stage typically are:
Requirements Specifications, Electronic Design
Architecture description, Electronic Design De-
tailed description. Results: VHDL files for HPDs.
Correctness of the design (Static Code Analy-
sis) and its compliance with the requirements
(Functional Testing) are verified after design
•
Synthesis (bringing in) of project scheme
may be efected using schematic editor (li-
brary of elements), hardware description
language or automaton state low graph ed-
itor. Functional modules may be developed
by various tools, but the data obtained are
then united into a single circuit list.
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