Field Programmable Gate Array Technology for NPP I&Cs - Nuclear Power Plant Instrumentation and Control Systems for Safety and Security - page 125

• Translation of data from Electronic Design

Interface Format (EDIF) Native Generic
Database (NGD) internal format.

The limitations as established by LogicLock
functions ensure identical arrangement when
logic block is performed within a current proj-
ect or transferred to another project. LogicLock
limitations may “lock” logic at a fixed position
within the device. LogicLock may also specify
a part of project logic for later optimization of
its arrangement in an IC. Addition of logic to a
project would not affect the properties of blocks
“locked” LogicLock limitations.
The process of design from project synthesis
to its realization in a crystal is fully supported
by CASE-tools (Melnyk, A. et al., 2007; Tam,
S., 2003) (Figure 3). The following is a short
description of six design process stages.

• Crystal mapping, i.e. transformation of

designed logic elements to their physical
counterparts.

• Placement of physical element and rout-

ing of their interconnections. On this stage
ModelSim tool is used for Veriication of
Netlist Files & Floor Plan Files generated by
Quartus II tool (Logic Simulation, Timing
Simulation, Static Timing Analysis).

Application of ModelSim to automate verifi-
cation environment allows significantly decrease
time of verification.
Compliance of developed FPGA-based I&C
system with the required functionality can be
verified with a testbed, which simulate inputs and
allows to test outputs and performance. National
Instruments LabView is an automated test software
that provides with the tools to create any testing,
measurement and control systems. It simplifies
system design by offering access to the newest
high-performance and low-cost entry points to
the reconfigurable I/O platform made by National
Instruments Corp., to one of the highest bandwidth
vector signal analyzers on digitizers on the market,
and to the latest off-the-shelf hardware.
Let us discuss Atera Quartus II tool in details.
Quartus II has such basic functional possibilities:
usage of hardware description language, project
scheme input, compilation, logic synthesis, full
timing and functional simulation, analysis of worst
timing case, logic analysis, device configuration
(Kharchenko, V. S., Sklyar, V. V. (Ed.), 2008).
Quartus II includes LogicLock step design
package, that permits laying destination of outputs
and timing parameters, test functionalities and
capacities of designed systems and then establish
limitations in order to “lock” (fix) arrangement
and characteristics of a specific logic block by
applying LogicLock limitations.

• Synthesis (bringing in) of project scheme

may be efected using schematic editor (li-
brary of elements), hardware description
language or automaton state low graph
editor.

Functional modules may be developed by vari-
ous tools, but the data obtained are then united
into a single circuit list.

1. Simulation is performed in order to test
functioning of the project scheme with zero
or single delays. Designer forms a diagram
of input actions (test vectors).
2. Development or correction of User Constraint
File implies description of requirements to
arrangement of components and timing rela-
tions of signals using an appropriate editor.
3. Project implementation in FPGA includes:
a. Translation of data from Electronic
Design Interface Format (EDIF) Native
Generic Database (NGD) internal
format;
b. Crystal mapping, i.e. transformation
of designed logic elements to their
physical counterparts;