Field Programmable Gate Array Technology for NPP I&Cs - Nuclear Power Plant Instrumentation and Control Systems for Safety and Security - page 123

Table 4. Characteristics of circuits of Cyclone III LS family (65nm technology)

Maximum Resource Count for Cyclone III LS FPGAs (1.2 V)

EP3CLS70 EP3CLS100 EP3CLS150 EP3CLS200

Resources LEs (K) 70 100 151 198

M9K memory blocks 333 483 666 891

Embedded memory (Kb) 2,997 4,347 5,994 8,019

18 x 18 multipliers 200 276 320 396

Architectural
Features

Global clock networks 20

PLLs 4

Configuration file size (Mb) 26.8 26.8 50.6 50.6

Design security yes

I/O voltage levels supported
(V)

1.2, 1.5, 1.8, 2.5, 3.3

I/O standards supported LVDS, LVPECL, Differential SSTL-18, Differential SSTL-2, Differential

HSTL, SSTL-18 (I and II), SSTL-2 (I and II), 1.5 V HSTL (I and II), 1.8 V
HSTL (I and II), PCI, PCI-X 1.0, LVTTL, LVCMOS

LVDS channels, 840 Mbps 169

On-chip termination (OCT) Series and differential

External Memory
Interfaces

Memory device supported DDR2, DDR, SDR

Figure 2. LAB structure of circuits of APEX II family