Environmental Engineering Reference
In-Depth Information
Table 3. Characteristics of circuits of Stratix IV E family (40nm technology)
 
Maximum Resource Count for Stratix IV E FPGAs (0.9 V)
 
EP4SE230
EP4SE360
EP4SE530
EP4SE820
Resources
ALMs
91,200
141,440
212,480
325,220
LEs (K)
228
354
531
813
Registers
182,400
282,880
424,960
650,440
M9K memory blocks
1,235
1,248
1,280
1,610
M144K memory blocks
22
48
64
60
MLAB memory (Mb)
2,850
4,420
6,640
10,163
Embedded memory (Kb)
14,283
18,144
20,736
23,130
18 x 18 multipliers
1,288
1,040
1,024
960
Architectural
Features
Global clock networks
16
Regional clock networks
64
88
88
88
Periphery clock networks
88
88
112
132
PLLs
4
12
12
12
Design security
yes
Configuration file size (Mb)
95
141
172
230
HardCopy series device support
yes
Others
Programmable Power Technology
I/O Features
I/O voltage levels supported (V)
1.2, 1.5, 1.8, 2.5, 3.3
I/O standards supported
LVTTL, LVCMOS, PCI, PCI-X, LVDS, mini-LVDS, RSDS,
LVPECL, Differential SSTL-15, Differential SSTL-18, Differential
SSTL-2, Differential HSTL-12, Differential HSTL-15, Differential
HSTL-18, SSTL-15 (I and II), SSTL-18 (I and II), SSTL-2 (I and II),
1.2 V HSTL (I and II), 1.5 V HSTL (I and II), 1.8 V HSTL (I and II)
Emulated LVDS channels,
1,100 Mbps
128
256
256
288
LVDS channels, 1,600 Mbps
(receive/transmit)
56/56
88/88
112/112
132/132
Embedded dynamic phase alignment
(DPA) circuitry
yes
On-chip termination (OCT)
Series, parallel, and differential
Memory devices supported
DDR3, DDR2, DDR, QDR II, QDR II+, RLDRAM 2, SDR
binatory functions registers are omitted (routing
performed without them), whereas LUT output
controls LE output.
Each LE has two outputs that control such
routing structures: local, MegaLAB or FastTrack
interconnections. Each output may be operated
irrespective from LUT or register output. For
instance, LUT may operate one output, while
register connects the other one. This property,
called “register packing,” permits application of
register and LUT to realize unconnected functions.
LE may also realize register and non-register
options of LUT output.
 
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