Environmental Engineering Reference
In-Depth Information
Table 2. Characteristics of circuits of Stratix V GS family (28nm technology)
Maximum Resource Count for Stratix V GS FPGAs (0.85 V)
5SGSD3
5SGSD4
5SGSD5
5SGSD6
5SGSD8
Resources
ALMs
89,000
135,840
172,600
220,000
262,400
LEs (K)
236
360
457
583
695
Registers
356,000
543,360
690,400
880,000
1,049,600
M20K memory blocks
688
957
2,014
2,320
2,567
M20K memory (Mb)
13
19
39
45
50
MLAB memory (Mb)
2.72
4.15
5.27
6.71
8.01
Variable-precision digital
signal processing (DSP)
blocks
600
1,044
1,590
1,775
1,963
18 x 18 multipliers
1,200
2,088
3,180
3,550
3,926
Architectural Features
Global clock networks
16
Regional clock networks
92
Design security
yes
I/O Features
I/O voltage levels supported
(V)
1.2, 1.5, 1.8, 2.5, 3.3
I/O standards supported
LVTTL, LVCMOS, PCI, PCI-X, LVDS, mini-LVDS, RSDS,
LVPECL, Differential SSTL-15, Differential SSTL-18, Differential
SSTL-2, Differential HSTL-12, Differential HSTL-5, Differential
HSTL-18, SSTL-15 (I and II), SSTL-18 (I and II), SSTL-2 (I and II),
1.2 V HSTL (I and II), 1.5 V HSTL (I and II), 1.8 V HSTL (I and II)
LVDS channels, 1.4 Gbps
(receive/transmit)
108
174
174
210
210
Embedded dynamic phase
alignment (DPA) circuitry
yes
On-chip termination (OCT)
Series, parallel, and differential
Transceiver count (14.1
Gbps)
24
36
36
48
48
PCIe hard IP blocks (Gen3)
1
1
1
2
2
Memory devices supported
DDR3, DDR2, DDR, QDR II, QDR II+, RLDRAM II, RLDRAM 3
the number of available lines and columns of
interconnections, thus ensuring their high flexibil-
ity.
LE is the smallest part of logic in APEX II
architecture. Each LE contains a LUT conversion
table with four inputs that serves as a functional
generator able of quick realization of any four-
variables function. Besides, each LE includes a
programmable register and transfer and staging
circuits.
Each programmable register in LE may be
configured to operate as a D, T, JK or SR trigger.
Register timing and cleanup control signals may
be accessed using global signals, general purpose
I/O leads or any internal logic. To realize com-
Each LAB comprises a predestined logic to
manage control signals to LEs and ESBs. Control
signals may be timing, timing enable, asynchro-
nous reset, pre-installation and loading, synchro-
nous cleanup and synchronous boot. Maximum
six signals may be passed simultaneously. Though
synchronous boot and cleanup signals are mainly
used for counter realization, they may perform
other functions as well.
Search WWH ::
Custom Search