Environmental Engineering Reference
In-Depth Information
Table 1. Continued
Maximum Resource Count for Arria 10 GX FPGAs
I/O Features
I/O voltage levels supported (V)
1.2, 1.25, 1.35, 1.8, 2.5, 3.0
I/O standards supported
3 V I/Os Only: 3 V LVTTL, 2.5 V CMOS
DDR and LVDS I/Os: POD12, POD10, Differential POD12, Differential
POD10, LVDS, RSDS, mini-LVDS, LVPECL
All I/Os: 1.8 V CMOS, 1.5 V CMOS, 1.2 V CMOS, SSTL-18 (I and II),
SSTL-15 (I and II), SSTL-135, SSTL-125, SSTL-12, HSTL-18 (I and II),
HSTL-15 (I and II), HSTL-12 (I and II), HSUL-12, Differential SSTL-18 (I
and II), Differential SSTL-15 (I and II), Differential SSTL-135, Differential
SSTL-125, Differential SSTL-12, Differential HSTL-18 (I and II),
Differential HSTL-15 (I and II), Differential HSTL-12 (I and II), Differential
HSUL-12
LVDS channels, 1.6 Gbps
(receive/transmit)
120
120
168
168
222
Embedded dynamic phase
alignment (DPA) circuitry
yes
On-chip termination (OCT)
Series, parallel, and differential
Transceiver count
12
12
24
24
36
PCI Express® (PCIe®)
hard IP blocks (Gen3)
1
1
2
2
2
Memory devices supported
DDR4, DDR3, DDR2, QDR IV, QDR II+, QDR II+ Xtreme, LPDDR3,
LPDDR2, RLDRAM 3, RLDRAM II, LLDRAM II, HMC
10AX057
10AX066
10AX090
10AX115
I/O voltage levels supported (V)
1.2, 1.25, 1.35, 1.8, 2.5, 3.0
I/O standards supported
3 V I/Os Only: 3 V LVTTL, 2.5 V CMOS
DDR and LVDS I/Os: POD12, POD10, Differential POD12, Differential
POD10, LVDS, RSDS, mini-LVDS, LVPECL
All I/Os: 1.8 V CMOS, 1.5 V CMOS, 1.2 V CMOS, SSTL-18 (I and II),
SSTL-15 (I and II), SSTL-135, SSTL-125, SSTL-12, HSTL-18 (I and II),
HSTL-15 (I and II), HSTL-12 (I and II), HSUL-12, Differential SSTL-18 (I
and II), Differential SSTL-15 (I and II), Differential SSTL-135, Differential
SSTL-125, Differential SSTL-12, Differential HSTL-18 (I and II),
Differential HSTL-15 (I and II), Differential HSTL-12 (I and II), Differential
HSUL-12
LVDS channels, 1.6 Gbps
(receive/transmit)
270
270
384
384
Embedded dynamic phase
alignment (DPA) circuitry
yes
On-chip termination (OCT)
Series, parallel, and differential
Transceiver count
48
48
96
96
PCI Express® (PCIe®)
hard IP blocks (Gen3)
2
2
4
4
Memory devices supported
DDR4, DDR3, DDR2, QDR IV, QDR II+, QDR II+ Xtreme, LPDDR3,
LPDDR2, RLDRAM 3, RLDRAM II, LLDRAM II, HMC
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