Environmental Engineering Reference
In-Depth Information
Table 1. Characteristics of circuits of Arria 10 GX family (20nm technology)
Maximum Resource Count for Arria 10 GX FPGAs
10AX016
10AX022
10AX027
10AX032
10AX048
Resources
ALMs
61,510
81,510
101,620
119,660
182,720
LEs (K)
160
220
270
320
480
Registers
246,040
326,040
406,480
478,640
730,880
M20K memory blocks
440
583
750
891
1,438
M20K memory (Mb)
9
11
15
17
28
MLAB memory (Mb)
1
1.4
2.2
2.9
4.4
Variable-precision digital signal
processing (DSP) blocks
156
192
800
985
1,368
18 x 19 multipliers
312
384
1,600
1,970
2,736
10AX057
10AX066
10AX090
10AX115
ALMs
217,080
251,450
339,620
427,700
LEs (K)
570
660
900
1,150
Registers
868,320
1,005,800
1,358,480
1,710,800
M20K memory blocks
1,850
1,964
2,339
2,713
M20K memory (Mb)
36
39
46
54
MLAB memory (Mb)
5.0
5.7
9.2
12.7
Variable-precision digital signal
processing (DSP) blocks
1,612
1,855
1,518
1,518
18 x 19 multipliers
3,223
3,356
3,036
3,036
10AX016
10AX022
10AX027
10AX032
10AX048
Architectural
Features
Global clock networks
32
Regional clock networks
8
8
8
8
8
Design security
Bitstream encryption with authentication
10AX057
10AX066
10AX090
10AX115
Global clock networks
32
Regional clock networks
8
16
16
16
Design security
Bitstream encryption with authentication
10AX016
10AX022
10AX027
10AX032 10AX048
continue
d on following page
CASE Quartus II compiler places the project-
associated logic within LABs or LAB auxiliary
blocks, thus permitting usage of quick-acting local
interconnections to increase the capacity of system
designed. APEX FPGAs use LAB intermittent
structure in such a way that each LAB is able to
control two areas of local interconnections.
Each LAB structure may control thirty LEs
using quick-acting local interconnections. Figure 2
shows LAB structure for APEX II family FPGAs.
Each LE controls left or right area of local
interconnections intermittent by LEs, whereas а
local interconnection controls LEs within its own
LAB or adjacent LABs. This property optimizes
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