Field Programmable Gate Array Technology for NPP I&Cs - Nuclear Power Plant Instrumentation and Control Systems for Safety and Security - page 118

CPLD architecture has its origins in Program-
mable Arrays Logic (PAL) preceded by Program-
mable Logic Arrays (PLA) and from Generic
Arrays Logic (GAL). Its functional unit consists
of microcells, each of them performing some
combinatory and/or register functions. Func-
tional logic within the block is a matrix of logic
products (terms). A subset of terms may be ac-
cessed by each macrocell via term distribution
diagram. Switch matrix commutates the signals
coming from outputs of the functional unit and
I/O unit. As distinct from FPGA (segmented con-
nections), CPLDs have a continuous system of
connections (completely commuted connections).
FPGA architecture topologically originates
from channeled Gates Arrays (GA). In FPGA
internal area a set of configurable logic units is
disposed in a regular order with routing channels
there between and I/O units at the periphery. Tran-
sistor couples, logic gates NAND, NOR (Simple
Logic Cell), multiplexer-based logic modules,
logic modules based on programmable Look-
Up Tables (LUT) are used as configurable logic
blocks. All those have segmented architecture of
internal connections.
System-On-Chip (SOC) architecture appeared
due to two factors: high level of integration per-
mitting to arrange a very complicated circuit on
a single crystal, and introduction of specialized
hardcores into FPGA. Additional hardcores may
be:

FPGA resources and additional RAM are
disposed at the processor address space. The ex-
amples of such solutions are the families of Altera
Excalibur (Embedded Processor Programmable
Solution), Atmel FPSLIC AT94 (Field Program-
mable System Level Integration Chip).
Tables 1-4 specify the main characteristics
of modern FPGA chips from Altera (for more
information see altera.com).
Manufacturer guarantees pre-sale testing of
100% FPGAs.
Unlike projects based on Applications Specific
Integrated Circuit (ASIC), which have a fixed
architecture (fixed IC outlets, IC functionality
cannot be altered), FPGAs are reconfigurable.
FPGAs (when the system is fed) are configured
by data stored at the configuration device or by
those supplied from the system controller. Altera
CASE-tools enable programming of devices
within the system. They configure FPGA with a
consecutive flow of data.
Moreover, FPGAs comprises an optimized
interface using microprocessors for serial or
parallel, synchronous or asynchronous configura-
tion of those devices. This interface also enables
microprocessors to interpret FPGAs as memory
and to configure them by recording to memory
cell virtual address, thus facilitating the recon-
figuration process.
FPGAs consist of several MegaLAB structures.
Each MegaLAB comprises 16 LAB - Logic Arrays
Blocks, one built-in systemic memory - Embedded
System Block (ESB) and a MegaLAB connection
which routes signals within the structure between
MegaLAB structures and I/O leads via FastTrack
connection. Besides, LAB signal fronts may be
controlled via local connection using I/O leads.
Each LAB comprises ten Logic Elements
(LE), auxiliary transfers of logic elements and
stage circuits, LAB control signals and a local
interconnection that transmits signals between
LEs in the same or an adjacent LAB as well as to
IOE or ESB cells.

• Additional Random Access Memory
(RAM) units.

• JTAG interface for testing and

coniguration.

• Phase-Locked Loop (PLL): Frequency

control system to correct timing relations
of clock pulses as well as for generation of
additional frequencies.

• Processor cores enabling creation of de-

vices with a control processor and a
peripheral.