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S
1
S
0
S
0
S
1
S
3
S
2
S
2
S
3
S
1
S
3
Fig. 13. The Sequential Signal Distribution Network (SSDN). This device routes and
distributes the bits of the current state (available at the output of the next state decoder) and
makes them available (20 clock cycles later) at the inputs of the next state decoder. The output
decoder, which is not required in all cases, is not shown in this figure.
the signal vertically through unpolarized horizontal wires (just like the SDN in the
previous section, but moving in upward instead of rightward). These signals then
complete the loop by moving leftward along the top of the next state decoder, and then
copies of the signals are distributed as needed to the next state decoder by a number of
horizontal lines (six, in this case). The particular signal that is applied to each of the
inputs of the next state decoder is determined by the pattern of clock phases that
appears on each horizontal line. S
0
, which has the shortest distance to travel, will
appear on the far-left vertical line after seven clock cycles, and so it needs to move
more slowly along the horizontal line than, say, S
3
, which appears on the far-left
vertical line after 19 clock cycles. This Sequential Signal Distribution Network
(SSDN) delivers all four bits of the current state to all necessary inputs of the next
state decoder 20 clock cycles after they appear at the output of the next state decoder.
By reassigning clock regions along the topmost wire down to the S
0
output, this
number could be reduced to as few as 14 clock cycles or, more generally, 3N + 2
clock cycles, where N is the number of bits in the current state.
5
Conclusions and Summary
This work has introduced two versions of a signal distribution network for QDCA
systems, one for combinational devices and the other for sequential devices. The
combinational SDN block can accept an arbitrary number of inputs and yield an
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