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equally arbitrary number of distributed signals, which can then be forwarded to a
combinational logic block without the need for additional wire crossings.
Regardless of the number of inputs, the combinational SDN requires only four
highly regular clock signals, and the signal distribution function for a device with N
inputs is always completed in 4N - 2 clock cycles.
The wire crossings in the combinational SDN rely only on the strongest interac-
tions available in QDCA systems—the interactions between near-neighbor cells along
the same line. For this reason, the excitation energy of the system should not be
degraded by the use of the SDN, which means that systems using it will exhibit
thermal behavior and tolerance of fabrication imperfections very similar to that of
other robust QDCA wires and gates.
The sequential SDN fills the same role, distributing multiple copies of an arbitrary
number of bits, but it does so in an optimized manner for sequential devices.
It implements the required wire crossings that must occur at the output of the next
state decoder, while also distributing those bits to the necessary locations at the input
of the next state decoder. It can perform this task in as little as 3N + 2 clock cycles,
where N is the number of bits in the current state.
Acknowledgment. This work was supported by the Leitha and Willard Richardson Profes-
sorship of Engineering, which is provided by the Valparaiso University College of Engineering.
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