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AC
in
M
M
M
Sum
M
M
C
out
Signal
Distribution
Network
Combinational
Logic
Fig. 8. A schematic of the circuit used to perform one-bit full addition using QDCA cells. This
circuit takes full advantage of the majority logic functionality of the QDCA cell to minimize the
number of gates needed.
A
B
C
in
M1
X1
X2
X3
M2
M5
Sum
M3
M4
C
out
Signal
Distribution
Network
Combinational
Logic
Fig. 9. A QDCA implementation of the schematic circuit shown in Fig.
8
. The three vertical
wires carry the three inputs, and these three inputs must all arrive at the majority logic gates
(M1-M4) at the same time. This is done by adjusting the clock phases of the horizontal lines.
Figure
10
shows that the three-input SDN with associated combinational logic
gates can still be implemented using only four clock signals, and that those clock
signals still exhibit the highly regular pattern of behavior first seen in Fig.
5
.
Figure
11
shows the data traces for labeled cells in Fig.
9
for the case where
A = 1, B = 0, and C
in
= 1. This figure illustrates that the three inputs are once again
applied only during the first clock cycle, and that these signals flow from left to right
along the horizontal wires (such as the one including cells X1, X2, and X3).
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