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Polarizaion
1
0
X
Y
Cell #1
Cell #2
Cell #3
AND1
1
0
0
1
0
1
0
1
0
AND2
0
Out
1
11
1
2
3
4
5
6
7
8
9
10
Clock Cycle
Fig. 6. The states of labeled cells throughout the operation of the device in Fig.
4
(b) when
X = 1 and Y = 0. Inputs X and Y are only applied during the first clock cycle, and their
contents are propagated through the device at different speeds so that they arrive at AND1 and
AND2 at the same time. The output correctly shows that 1
0 = 1.
X
Y
X
Y
X
Y
a)
b)
c)
OUT
OUT
OUT
T=1
T=5
T=4
X
Y
X
Y
d)
e)
OUT
OUT
T=6
T=9
Fig. 7. Snapshots of the XOR gate with SDN at key points during its operation. (a) At T = 1,
the left-hand vertical wire contains X = 1, while the right-hand vertical wire contains Y = 0.
(b) At T = 4, input X has propagated to the cell indicated with the arrow. (c) At T = 5, this cell
drives the right vertical wire by its interaction with the indicated cell. Note that input Y is
unpolarized at this time. (d) At T = 6, the value of input X has propagated through the vertical
wire and is quickly transmitted to both AND gates, where input Y just has arrived. (e) At T = 9,
the device delivers the correct output.
3
Expanding the Signal Distribution Network
Although the previous example focused on a two-input device, the benefits of the SDN
become much more apparent when this is expanded to a three-input device. Figure
8
shows a schematic representation of a full adder, which was originally introduced in
Ref. [
5
].
Figure
8
once again demonstrates a separation of the signal distribution function
from the combinational logic gates, and Fig.
9
illustrates how the two-input SDN can
be expanded to three inputs in order to implement the circuit shown in Fig.
8
.
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