A Clocking Strategy for Scalable and Fault-Tolerant QDCA Signal Distribution in Combinational and Sequential Devices - Field-Coupled Nanocomputing: Paradigms, Progress, and Perspectives - page 61

Barrier Height

Locked Locked Locked

Region 1

Re laxed Re laxed

Region 2

Region 3

Region 4

Clock Cycle

Fig. 2. Data propagation through four adjacent quasi-adiabatically switched regions. The clock
signals are phase-shifted to ensure that as each region enters the ''locking'' phase, the cells in
the previous region are in the ''locked'' phase. This causes the data to be shifted from one region
to the next, as indicated by the arrows.

neighbor interactions, which will increase the excitation energy of the device and in
turn will improve its thermal behavior and its tolerance for fabrication imperfections.
Furthermore, the SDN can be scaled to handle combinational devices with any number
of inputs and any number of outputs, typically with fewer cells and using less surface
area than other candidate solutions. Additionally, it requires only four clock signals,
each of which exhibits a very regular pattern of transitions regardless of the function
being implemented. Finally, we will see that the SDN is guaranteed to handle the
signal distribution functionality for an N-input device in no more than 4N - 2 clock
cycles, meaning that the entire combinational device will require approximately 4N
clock cycles, depending on how the clock signals are used in the binary logic portion
of the device [ 16 ].
The block diagram shown in Fig. 3 illustrates the operation of the SDN. The
system separates the wire crossings from the logical operations, allowing each of the
two blocks to be optimized. Once the SDN has done its work, the distributed signals
are applied to the combinational logic gates, and there is no need for any wires to cross
within that region. Separating the signal distribution from the combinational logic
gates allows the optimization of the SDN and the combinational logic gates sepa-
rately, leading to a more efficient and much more scalable solution.

Inputs

Distributed
Signals

Output s

Signal
Distribution
Network

Combinational
Logic Gates

Fig. 3. Separation of the function into signal distribution and combinational logic. This
separation allows for the use of an optimized, highly regular signal distribution network,
followed by a similarly optimized combinational logic block without the need for interspersed
wire crossings. The number of inputs, distributed signals, and outputs are entirely arbitrary in
this figure.