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60 nm
Fig. 1. The QDCA geometry studied in this work. Each cell is composed of four quantum dots,
with two electrons sharing each four-site cell. Sites are each 20 nm from the center of the cell,
and adjacent cells are 60 nm apart. Tunneling is allowed between adjacent sites within the cell,
and electron repulsion leads to a bistable alignment into one of two states, which are used to
encode a binary 0 and a binary 1.
same direction. In the system studied in this work, the corners of the cells are 20 nm
from the center, and the centers of adjacent cells are 60 nm apart.
By carefully arranging the location of QDCA cells, it is possible to create a
majority logic gate, which is further capable of functioning as either an AND or an OR
gate [
5
]. Combining these gates with the QDCA cell configuration of an inverter, any
combinational logical device can be constructed from QDCA cells [
6
]. A very active
area of QDCA research involves the design and verification of complex devices
composed of the fundamental QDCA gates [
10
-
15
]. Invariably, these more complex
devices require a number of binary wires to transmit signals between the logic gates,
and these wires often need to cross each other. Due to the coplanar nature of the
QDCA architecture, these wire crossings present a special challenge. The purpose of
this work is to demonstrate a comprehensive solution to this wire crossing problem.
In addition to carefully considering the placement of each cell in a QDCA device,
the designer must also determine the timing of clock signals applied to the device, along
with which cells will be attached to those clock signals. These clock signals control the
tunneling barriers within each cell, and they are switched quasi-adiabatically.
The tunneling barriers of each cell are raised and lowered smoothly to control how and
when each cell responds to its neighbors. The tunneling barriers are typically modulated
through four stages: the locking state, in which the tunneling barriers are raised; the
locked state, in which tunneling is entirely restricted by the presence of high barriers;
the relaxing state, during which tunneling barriers are lowered; and the relaxed state, in
which tunneling barriers are held very low, allowing nearly free electron movement
within a cell.
This natural sequence of four clock signals is shown in Fig.
2
, which illustrates the
flow of data through four adjacent clocking regions by the careful timing of the clock
signals. The arrows demonstrate the flow of information from one region to the next.
2
The Signal Distribution Network
The signal distribution network (SDN) is a possible solution to the wire crossing
problem. This device has many significant benefits over the wire-crossing solutions
that have been previously presented. Most importantly, it relies entirely on nearest
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