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X
Y
a)
OUT
Signal
Distribution
Network
Combinational
Logic
X
Y
AND1
Cell #2
OR
Cell #3
b)
OUT
Cell #1
AND2
Signal
Distribution
Network
Combinational
Logic
Fig. 4. An implementation of an XOR device using a minimal signal distribution network.
(a) A schematic representation of the function being implemented, which is logically identical
to that shown in Fig. 4 . (b) The layout of QDCA cells used to implement the function. Cell #2 is
driven by input Y in the first clock cycle. Input X is conveyed along the horizontal line for four
cycles until it reaches Cell #1. Cell #1 is then used to drive Cell #2 (and the vertical line it is a
part of) in the fifth cycle. This is made possible by removing input Y during the second cycle.
This implementation uses only four different clock signals and eight clock cycles to complete
the calculation.
As an example of this type of structure, consider the circuit shown in Fig. 4 , which
separates the signal distribution function from the logic gates as described above.
The resulting benefits of this change are quite significant. The SDN-based device
shown in Fig. 4 will require only four clock signals, rather than the seven that were
required for an earlier design of this circuit that did not use the SDN [ 16 ]. Further-
more, as can be seen in Fig. 5 , the clocking pattern of these four clock signals is
entirely regular, which significantly simplifies the clock generation.
The operation of this new type of wire crossing merits a detailed description. The
two inputs, labeled X and Y in Fig. 4 (b), each drive a long vertical binary wire in the
first clock cycle. The rightmost wire (initially carrying input Y) is already at the right
edge of the SDN, so any required copies of that signal can be simply be connected
from that vertical line at the required location. However, any necessary copies of the
leftmost vertical binary wire (initially carrying input X) will need to cross over the
other vertical binary wire before they can be used in the combinational logic gates.
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