Reversible and Adiabatic Computing: Energy-Efficiency Maximized - Field-Coupled Nanocomputing: Paradigms, Progress, and Perspectives - page 350

(a) (b)

Fig. 8. (a) Definition of logic density in QCA, the average gate area expressed as a multiple of
molecular cell footprints. (b) Maximum operating frequency of QCA circuits as a function of
cell width, for A = 300w 2 , 200w 2 , and 100w 2 dissipation area per majority gate. High-density
computer arithmetic designs found in the literature typically use about 200 cell footprints of
circuit area per each logic gate (the middle curve) [ 8 ].

in standard CMOS layout rules, enabling us to express scalable QCA layout
lengths/distances as a multiple of w. Based on the selection of arithmetic units found in
literature, we calculated the average area A available for each standard gate, which in
QCA is a 3-input Majority Voter Gate (MG) residing in an imaginary layout rectangle
of area A, as illustrated in Fig. 8 (a). We found that the average area per gate inside the
densest core logic (e.g. a full adder) was around A = 100w 2 , while the wiring overhead
of an optimized multi-bit arithmetic unit increased the area per gate typically to
A = 200w 2 . In random logic, the area per gate was typically to A = 300w 2 [ 8 ].
Figure 8 (b) shows the resulting maximum operating frequency vs. QCA cell width
w, when the heat generation is limited to 100 W/cm 2 . In this comparison, the nominal
area per logic gate was considered to be A = n fp w 2 , where the gate span n fp was 300,
200, or 100 cell footprints, corresponding to the studied relative gate densities.

Table 3. Estimates for the worst-case bit erasures in QCA arithmetic units, vs. operand word
length n. The logical operations must perform only a linear number of erasures, but the adders
discard 2-6 times that much and the multipliers a square-law amount of information [ 8 ].

Binary addition with unsigned n-bit operands (typically linear)
Theoretical addition operation n

Ripple carry adder, lower bound 2n

Ripple carry adder, upper bound 6n

Binary multiplication with unsigned n-bit operands (typically square-law)
Theoretical complete multiplication n + 1

Theoretical non-trivial multiplication 123 9 log(n + 241) - 673

8n 2 Array multiplier

16n 2 Serial-parallel multiplier

16n 2 Serial-parallel optimized multiplier - 12n

26n 2 + 86n - 2 Radix-4 recoded multiplier