Reversible and Adiabatic Computing: Energy-Efficiency Maximized - Field-Coupled Nanocomputing: Paradigms, Progress, and Perspectives - page 349

Table 2. Bit erasures of the standard gate set {not, nand, nor, xor} for each operand combi-
nation, and the number N i of each gate in the design and the weighted average gate erasures
R avg,j .

Inputs Output Information loss

a not(a)

0 1 log 2 (1) = 0 bits

1 0
N not = 18, R avg,not = 0 bits/gate

a b nand(a,b)

0 0 1 log 2 (3) & 1.585 bits

0 1 1
1 0 1
1 1 0 log 2 (1) = 0 bits
N nand = 49, R avg,nand =(33 1.585 + 1 3 0)/4 & 1.19 bits/gate

a b nor(a,b)

0 0 1 log 2 (1) = 0 bits

0 1 0 log 2 (3) & 1.585 bits

1 0 0
1 1 0
N nor = 19, R avg,nor =(130+33 1.585)/4 & 1.19 bits/gate

a b xor(a,b)

0 0 0 log 2 (2) = 1 bit

0 1 1
1 0 1
1 1 0
N xor = 4, R avg,xor = 1 bit/gate

6 Predictions for Future Technologies

Reversible logic has great potential in the Beyond-CMOS technologies, while quasi-
adiabatic CMOS can operate reasonably well with less concern for the information
loss [ 13 ]. For asymptotically adiabatic circuits in either CMOS like our ALU, or in
one of the emerging technologies including QCA [ 2 ], logical reversibility is a pre-
requisite for reaching the full potential of recovering all energy. Our previous work on
QCA arithmetic units can be used to predict the operating frequency limits of the
studied ALU, if implemented in the emerging extreme low-power technologies [ 8 ].
We determined the average logic density of adders and multipliers based on
cellular automata, assuming a constant-width square cell as the basic device con-
ceptualized in Fig. 8 (a). The cell width w was used as a measurement unit similar to k