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The typical gate span was n
fp
= 200 footprints and the area A = 200w
2
in the studied
optimized arithmetic layouts. The results indicate that irreversibility heat is limiting
the operating frequency of nanometer-scale molecular QCA cells, while possible
sparser implementations will suffer less.
The existing computer arithmetic designs have not been optimized for logical
reversibility, which is apparent from the conclusions of our previous study summa-
rized in Table
3
. The fundamental baseline information loss for binary addition is
n bits, where n is the operand word length of the arithmetic unit. The 4-bit CMOS
ALU unit in this paper discards about 85 bits per operation in the irreversible mode,
while the known basic adder structures for QCA would have between 8-24 bit era-
sures per operation. However, the Bennett-clocked reversible CMOS ALU discards
only 8 bits, which appears to be the ultimate lower bound even for the future
technologies.
7
Conclusion
The adiabatic charging and reversible computing approaches are related to each other,
and both will eventually be necessary for the efficient design of future digital circuits
in the emerging technologies. In this paper, we considered the relationship between
adiabaticity and information loss and designed a configurable CMOS ALU with
irreversible and reversible operation modes. The results indicate that even using
standard CMOS devices, adiabatic charging and reversible Bennett-clocking together
would potentially yield, on average, one or two orders of magnitude improvement in
power consumption, compared to the standard static CMOS approach.
The presented adiabatic CMOS design relies on local interaction between the
consequent states and we consider it a prototype for future reversible circuits espe-
cially based on quantum-dot cellular automata. The existing computer arithmetic
structures appear sub-optimal from the perspective of information loss, even though
the Bennett-clocked circuit can reach the theoretical lowest bound of loss in the
addition operation. The cost in throughput and clocking complexity suggests that a
block-reversible scheme should be utilized in larger designs, to seek a compromise
between information conservation and the design complexity.
Acknowledgments. The authors wish to thank the organizers and attendees of the Workshop
on Field-Coupled Nanocomputing, February 7-8, 2013, Tampa, Florida, USA, for their sug-
gestions and constructive critique on the design of emerging reversible circuits. This work was
supported by the Academy of Finland under research grant 132869 and the Finnish Foundation
for Technology Promotion.
References
1. International Technology Roadmap for Semiconductors. ITRS report [Online] (2012).
2. Lent, C., Tougaw, P.: A device architecture for computing with quantum dots. Proc. IEEE
85(4), 541-557 (1997)
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