ToPoliNano: NanoMagnet Logic Circuits Design and Simulation - Field-Coupled Nanocomputing: Paradigms, Progress, and Perspectives - page 276

Fig. 6. Simulation of NML circuits. While physical simulators provide the most accu-
rate simulation they can be used only on small circuits. At the same time, VHDL model
gives inaccurate results for the loss of information regarding circuits layout. ToPoli-
Nano was created to overcome these problems and to provide a tool that allows to have
both accurate results and fast simulation of complex circuits.
methodology used in CMOS circuits. This means to describe circuits of any kind
of complexity using VHDL language, to automatically generate the layout and
to fast simulate the obtained circuit. For this emerging technology there are
no tools available to perform these analysis, therefore it has been necessary to
design a completely new system. The structure of Topolinano is shown in Fig. 7 .
-The Logic Synthesizer is the first block encountered in the traditional
CMOS design flow. Starting from a generic VHDL description it translates
it on a specific logic gates set. In this case it takes an entry VHDL file and
it generates another VHDL file with a structural description, that means the
circuit is described only using the set of gates available in this technology
(majority voter, and, or, inverter). The logic synthesizer is still partially in
development.
-The Parser takes the structural VHDL file generated by the logic synthesizer
and creates an in-memory representation of the circuit itself. The internal
description is based on a hierarchical graph to eciently handle the circuits in
terms of both time and memory occupation on the host computation machine.
The parser is complete and it is throughly described in Sect. 3 .
-The Place & Route takes the graph generated by the parser and automat-
ically creates the circuit layout. This block is still in development, as up to
now it can handle only combinational circuits of any complexity but not