ToPoliNano: NanoMagnet Logic Circuits Design and Simulation - Field-Coupled Nanocomputing: Paradigms, Progress, and Perspectives - page 275

Fig. 5. VHDL model for NML circuits. (A) Example of NML circuit. (B) RTL model
described with VHDL. Registers are used to simulate the propagation delay while
ideal logic gates are used to model the logic function. (C) Clock signals applied to each
register.
missed. We have therefore created our own tool, ToPoliNano, Torino Politecnico
Nanotechnology tool [ 36 ], a tool targeted to design and simulation of Nano-
Magnet Logic circuits. ToPoliNano emulates the top-down approach used in
CMOS design, where circuits are described using the VHDL language and the
layout is automatically generated. Circuits can be simulated and important infor-
mation on the circuit behavior and the power consumption can be extracted,
knowing exactly the circuit area and the precise placement of every element
[ 37 ]. Mostly important the open and modular structure of the software allows
to easily integrated others emerging technologies, like we have done with Sili-
con Nanowires NanoPLA [ 38 , 39 ], making it the ideal platform for the study of
emerging technologies.
2.1 Tool Overview
ToPoliNano has been developed in C++ and is built around the idea to give to
researcher the possibility to design NML circuits following the same top-down