ToPoliNano: NanoMagnet Logic Circuits Design and Simulation - Field-Coupled Nanocomputing: Paradigms, Progress, and Perspectives - page 277

VHDL

Logic Synthesizer

Parser Manual Circuit

Description

Place & Route

Simulation

Switch

Power

Area

Fig. 7. ToPoliNano structure. Circuits are described through VHDL, a logic synthesizer
maps the circuit on the technology library available and a parser generates the in-
memory description. The layout can be generated automatically or manually, circuits
are then simulated obtaining data on the circuit behavior, the area occupied and the
power consumption estimation.

sequential. The circuit layout is based on the clock zones layout described in
Sect. 1 and shown in Fig. 4 (B). Section 4 provides more details on the Place &
route in its current state.
- It is also possible to Manually Describe circuits with a full custom approach.
This possibility is granted for two important reasons, because the Place &
Route block is still in development and because, no matter what level of
development the Place & Route block will reach, in certain cases the hand
of a designer is requested to reach the maximum level of optimization. Up to
now circuits can be described either directly writing the code that describes
the circuit or using external vectorial graphic editors and then importing the
circuit in ToPoliNano. Further details are given in Sect. 6 .
- Once the circuit layout is generated, a Simulator is used to verify the correct
behavior of the circuit. The algorithm used is based on a behavioral model
extracted from low level simulations. This tool is designed for high complexity
circuits (million of magnets), so only a behavioral algorithm allows a fast
enough simulation. However, since the model is based on physical simulations
it still gives accurate results. More details on the simulation algorithm are
provided in Sect. 5 .