NanoMagnet Logic: An Architectural Level Overview - Field-Coupled Nanocomputing: Paradigms, Progress, and Perspectives - page 241

Fig. 21. Simulation comparison between the original circuit (A), the correct NML
circuit with additional loop (B), and the NML circuit without additional loop (C),
which gave the wrong result.

4 Interconnections

The final problem encountered in the design of complex circuits with Field-
Coupled technologies, is the strong impact of interconnections both on the prop-
agation delay and on the circuit area. Figure 22 shows the detailed layout of a
NML 8 bits comparator, that is part of an LDPC decoder for wireless signals
[ 43 - 45 ]. The circuit schematic is shown in Fig. 22 , while the decoder description
is not reported here because it is not relevant for this discussion. Details on the
architecture itself can be found in [ 43 ]. What it is important to understand is
that most of the area (up to 99 %) is occupied by interconnection area. This lay-
out is based on the technological constraints described in Sect. 1.1 , so in other
types of NML or QCA the impact of interconnections can be different. However
interconnections will always represent an important part of the circuit area. It is
worth noting again that in Field-Coupled devices more area means more delay
and more power consumption.
The reason of this problem comes from the nature of the technology itself,
which favors local interactions over neighbor elements, penalizing long intercon-
nect wires. A possible solutions is to use particular architectures, called systolic
arrays, that can greatly reduce the interconnections overhead. Systolic arrays