NanoMagnet Logic: An Architectural Level Overview - Field-Coupled Nanocomputing: Paradigms, Progress, and Perspectives - page 242

Fig. 22. Example of interconnection impact in complex NML circuits. The circuit,
reported schematically in the detail, is a 8 bit comparator used inside a wireless decoder.
are briefly described in Sect. 4.1 alongside techniques to optimize the design and
to improve performance.
4.1 Systolic Arrays
A Systolic Array (SA) is a network of Processing Elements (PEs), also called
“Cells”, that are locally interconnected and can work in parallel. SAs were first
introduced by Kung and Leiserson in 1978, who stated: “a systolic system is a
network of processors which rhythmically compute and pass data through the
system” [ 46 ]. Each PE receives data from neighboring cells or from outside and
outputs result to the outside or to near PEs. Two are the main concepts at the
basis of SAs: parallel computation (i.e. all PEs work in the same way on different
data) and local transmission of data (i.e. there are not global signals). In Fig. 23
three examples of SAs arrangements are shown: a bi-dimensional matrix-like
shape SA (a), a linear SA (b), and an SA with signals flowing in three different
directions (c). The shape is determined by a three design process steps: starting
from the algorithm description, the Dependence Graph (DG) is derived; this is
shrunk along one axis to obtain the Signal Flow Graph (SFG) which represents
the real shape of the SA. Finally, PE internal structure is derived.
In last decades, increasing operating frequency has been enough to sustain the
request of higher computational eciency of digital circuits, reducing the need of
parallel architectures; for this reason SAs have not represented an attractive solu-
tion. However, approaching the boundary limit for CMOS scaling [ 47 ], and thus
for frequency increase, parallel solutions are being exploited and SAs are back
in the limelight. They have been designed for image processing [ 48 - 50 ], signal
processing [ 51 - 53 ] and video algorithms (such as those for MPEG compression).
Recently, automatic tools that translate algorithms to SAs for FPGAs have been
explored [ 54 ]. Also, reconfigurable arrays, that are not application-specific, have