Security Issues in QCA Circuit Design - Power Analysis Attacks - Field-Coupled Nanocomputing: Paradigms, Progress, and Perspectives - page 216

Fig. 19. Calculated power dissipation of QCA OR gate for Landauer-clocked (L) and
Bennett-clocked (B) OR gates [ 31 ].

for additional circuit complexity [ 31 , 50 ]. Here the vulnerability of QCA circuits
under Bennett clocking [ 49 ] to power analysis attack is considered as the worst
case scenario for attackers.
The wave of Bennett clocking used in this study is described as follows [ 31 ]:

min 1

+ sin t
T c

, 1 ,

x
λ c

E c ( x, t )= E 0 − (25)

C

where x is the position of the bit information, t is the time, λ c is the spatial
width of the Bennett-clocked region and T c is the temporal clocking period.
The lower bound power is modelled by describing the relevant physics of QCA
switching in a thermal environment, which is illustrated in detail by Lent et al.
[ 31 ]. To implement QCA circuits with Bennett clocking as shown in Eq. ( 25 ),
only the timing of the clocking signals needs to be altered, in order to keep the
bit information in place using the clock until a computational block is finished;
then the information is erased during the reverse order of computation.
It has already been demonstrated that a QCA OR gate using Bennett clock-
ing produces very low and similar power consumption values for inputs with