Security Issues in QCA Circuit Design - Power Analysis Attacks - Field-Coupled Nanocomputing: Paradigms, Progress, and Perspectives - page 215

5 Discussion of Practical QCA Devices

The upper bound power model was derived for semiconductor QCAs. However, it
can also be extended for molecular and magnetic QCAs by using the appropriate
Hamiltonian in the derivation [ 30 ]. Therefore, the power analysis attack results
obtained in this chapter can also be applied to other QCA implementations
under best case scenario. Although the power consumption in QCA is very low,
for power analysis attacks, it is the power difference between transitions from
'0' '0') that is important since it

indicates a power dependence on the processed data. It has been shown that
cryptographic algorithms implemented in QCA with typical four-phase clocking
could be vulnerable to power analysis attack. However, this result is for a best
case scenario for attackers which assumes non-adiabatic switching.
In a more typical scenario, a smoother clock would be used, which would
reduce the power consumption of transitions from 0

→ '0' (or '1' → '1') and '0' → '1' (or '1' →

0) significantly
[ 30 ]. As shown in Fig. 4 , the real power consumption will be lower than the upper
bound. The difference between the dynamic power and static power is less and
the power dependence on the Hamming distance of the inputs is also reduced.
This will require more power data to reveal the key, which would enhance the
security. Also, no noise is considered in this work. In a practical situation,
noise will be present when measuring the power consumption, which will affect
the power analysis attack. Therefore, in practice using a smoother clock, the
security of QCA cryptographic circuits would be greatly enhanced. Also, even
if the power dependence on processed data is still measurable under a smoother
clock, the measurement of power consumption with a magnitude of eV is very
dicult and expensive. Power analysis attacks were proposed as a cheap attack
technique using readily accessible equipment. This may not be the case for future
QCA devices.

→ 1 (or 1 →

6 The Worst Case Scenario for Attackers-Bennett
Clocking

QCA circuits using typical quasi-adiabatic clocking perform irreversible comput-
ing. Landauer has shown that any logically irreversible operation must dissipate
at least K B Tln (2) per bit, independent of the operation speed [ 47 ]. However, if a
copy of the bit to be erased is reserved, the operation can dissipate an arbitrarily
small amount of energy [ 48 ]. Furthermore, Bennett extended Landauer's theory
by showing that any computation could be implemented as a logically reversible
operation [ 49 ]. In this research, the logically irreversible clocking is referred to
as Landauer clocking which is the typical quasi-adiabatic four phase clocking
and the logically reversible clocking is referred to as Bennett clocking. Although
the reversible computing theory has been proposed for almost four decades, no
concrete circuits exist as they are infeasible to implement in CMOS due to the
complexity involved in their design. However, QCA technology provides a practi-
cal platform for the realization of reversible computing without the requirement