STT-Based Non-Volatile Logic-in-Memory Framework - Field-Coupled Nanocomputing: Paradigms, Progress, and Perspectives - page 178

The main difference between the logic-in-memory architecture and MRAM
is the bit density. In this architecture, the MTJs are patterned with a spacing of
20 nm to allow effective coupling between their free layers. On the other hand,
in MRAM, the MTJs are placed much further apart to prevent any coupling
between them. The close spacing between MTJs in this architecture has also its
pros and cons. On one hand while it increases the bit density of the architecture,
on the other it reduces the available room for the access transistors underneath
the MTJs. This competing space requirement within the architecture generates a
design challenge that can be resolved with proper choice of: (i) CMOS technology
node; and (ii) integration between CMOS and MTJs. As a first step in this
direction, we selected 22 nm CMOS technology node for integration with metal 1
pitch of 64 nm [ 26 ]. The second step was to redesign the MTJ-CMOS integration,
which we have discussed in the next sections.
To best describe the architecture we will start with its salient features. We
then intend to follow up with greater details of cell classification, logic blocks
and write/clock/read techniques in the architecture.

4.1 Salient Features

50 nm 2 MTJ dimensions: These dimensions ensure that the free layer
of MTJs used in the architecture is single domain and is stable at room
temperature (RT). The dimensions were arrived from both micromagnetic
simulations in OOMMF [ 27 ] and LLG [ 28 ] software and our past fabricated
results [ 29 ]. The aspect ratio ensures that there are two stable magnetization
states for the free layer at RT. These states will be used to define 0 and 1. The
dimensions also take care that a reasonably low critical current is required to
switch the MTJs at RT.
2. MTJ placement in regular 2D grid: The MTJs in the architecture are laid
out into well-defined rows and columns with a 120 nm row pitch and a 70 nm
column pitch.
3. MTJ integration with 22 nm CMOS technology node: 22 nm CMOS technology
node is selected for integration of access transistors.
4. Access transistor integrated with every alternate MTJs in a row and column:
The smaller room for the access transistors together with the required drive
strength and the metal pitch requirement of 22 nm CMOS node allows inte-
gration of only one access transistors for every alternate MTJs in rows and
columns. Figure 5 ashowsa3 D view of the architecture. Figure 5 b shows a
cross-section of the architecture.
5. Bit, source and word lines to address the MTJs in the architecture: The word
lines are used to turn on/off the access transistors. They are located in metal
3 and run parallel to the columns of MTJs. The bit and source lines are
housed in metal 2 and 1 respectively and are used for row addressing as well
as supplying the writing, clocking and reading current when required (see
Fig. 5 a).

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