Information Technology Reference
In-Depth Information
Bit Line
[Metal layer2]
120
120
Word Line (WL)
Via
Free Layer
Free Layer
Free Layer
Bit Line (BL)
Fixed Layer
Fixed Layer
Fixed Layer
Via
Via
70
85
85
Source Line
240
Access
Transistor
Access
Transistor
Metal layer1
Source Line (SL)
110
Polysilicon
Polysilicon
Access Transistor
(a)
All dimensions are in nm.
(b)
Fig. 5. (a) 3 D view of the STT-based logic-in-memory architecture; (b) Cross-section
of the architecture with the metal pitches.
4.2 Cell Classification
The selective integration of access transistors give rise to two types of cells in
the architecture, which we will classify as:
1. MTJs with access transistors: To access these MTJs, an appropriate bias is
applied across the bit and source lines of the row in which the MTJs are
placed. Next the access transistors for the MTJs are turned on with the help
of their word lines. This completes the path for the current through the MTJs.
2. MTJs without access transistors: These MTJs are accessed through their bit
and source lines. Whenever a bias is applied across their bit and source lines,
all of these MTJs conduct.
These cells are futher categorized into input, logic and output cells on the
basis of their functionality and participation in logic. With the help of a 2-input
exclusive-OR layout (Fig. 6 ), we will explain the different cell categories and the
functionalities in the architecture.
1. Input cells: These are the MTJs with access transistors. They hold the inputs
to any logic function. We will discuss the details of how to write the inputs
into them in Sect. 4.3 . In Fig. 6 , X 1 , X 2 , X 3 and X 4 are the input cells.
For 2-input exclusive-OR operation, x 1 ⊕ x 2 = x 1 · x 2 + x 1 · x 2 , the following
values will be written into the input cells: X 1 = x 1 , X 2 = x 2 , X 3 = x 1 and
X 4 = x 2 .
2. Logic cells: These are the MTJs that compute the logic. They can be of
either types and they form the body of the logic. These MTJs are to be
clocked whenever a logic is to be computed. They get their values through
neighbor interaction after the clock is released from them. These cells are
further sub-categorized into the following:
(a) Gates: Just as in NML, the basic logic gates in this architecture are the
3-input majority voter ( f ( x 1 ,x 2 ,x 3 )= x 1 · x 2 + x 2 · x 3 + x 3 · x 1 ) and the
inverter ( f ( x 1 )= x 1 ). Together they form the universal minority logic
function. 2-input AND/OR can be derived from this majority function
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