Reversible Logic Based Design and Test of Field Coupled Nanocomputing Circuits - Field-Coupled Nanocomputing: Paradigms, Progress, and Perspectives - page 158

8 Proposed Multiplexer Conservative QCA
Gate(MX-cqca)

For many of the designs, the designer could potentially be interested in using
the testing advantages of conservative logic but saving the number of QCA cells.
Thus, in this work we propose a new conservative logic gate that is conservative
in nature but is not reversible. The proposed conservative logic gate is called
multiplexer conservative QCA gate(MX-cqca) and has 3 inputs and 3 outputs.
Mx-cqca has one of its outputs working as a multiplexer that will help in mapping
the sequential circuits based on it, while the other two outputs work as AND and
OR gates, respectively. The mapping of the inputs to outputs of the MX-cqca
is: i 0 i ₓ 1 +

o 0 = i 0 i 1 ; o 1 = i 1 i 2 ; o 2 = i 2 + i 3 , where i o , i 1 and i 2 are the inputs and

o o , o 2 are the outputs, respectively. Figure 21 shows the block diagram of

the MX-cqca gate. Table 3 shows the truth table of the MX-cqca gate. The table
verifies the gate's conservative logic nature, i.e., the numbers of 1s in the inputs
is equal to the number of 1s in the outputs. Figures 22 and 23 show the QCA
design and layout of the proposed MX-cqca gate. From the QCA design, we can
observe that the proposed MX-cqca gate requires 4 clocking zones and 5 majority
gates for its QCA implementation. Table 4 shows the comparison between the
proposed MX-cqca gate and the Fredkin gate in terms of area and number of
QCA cells. The table illustrates that MX-cqca is better than the existing Fredkin
gate for implementing multiplexer-based designs. The MX-cqca gate requires 5
majority voters and 218 QCA cells with an area of 0

o 1 and

71 um 2 . Thus, it has 1 less
majority gate, 1 less inverter, 11 % less QCA cells and 5.4 % less area compared
to the Fredkin gate.
We also modeled the QCA layout of the MX-cqca gate using the HDLQ
Verilog library for performing the fault testing. The HDLQ model of the QCA
layout of the Fredkin gate is shown in Fig. 24 . Thus it can be observe that
modeledQCAlayouthave4FOs,1INV,5CWs,8LSWsand5MVs.We
conducted exhaustive testing of the HDLQ model of the Mx-cqca gate with
8 input patterns in the presence of all possible single missing/additional cell
defects. Testing of the Mx-cqca gate generates 24 unique fault patterns at the
output, as shown in Table 5 .
From fault tables we can see that there are 9 fault patterns 3, 7, 13, 17, 19,
20, 22, 23, 24 that will produce the correct outputs for test vectors a0 and a7 (all
0s and all 1s) even when there is fault. Thus two test vectors a0 and a7 can only
provide 62.5 % fault coverage. Thus in order to give the test vectors 100 % fault

.

Fig. 21. Proposed MX-cqca gate